Design and Test of Digital Circuits by Quantum-DOT Cellular Automata

by Fabrizio Lombardi

Overview

This detailed reference characterizes various defect and failure mechanisms in both combinational and sequential QCA devices. The book presents new design methodologies that have been proposed for QCA and describes clocking schemes that reduce kink errors in QCA. This comprehensive volume identifies and investigates unique QCA timing constraints and sequential designs. As a basis for CAD implementation, the book proposes algorithms that assign clocking zones and stretch paths for delay matching. Additionally, you find a comprehensive nanotechnology survey, detailing the advantages and disadvantages of various technologies. Other key topics include tile-based modular design, new memory architectures, and future QCA research directions.

Product Details

ISBN-13:	2901596932677
Publisher:	Artech House, Incorporated
Publication date:	11/28/2007
Edition description:	New Edition

Table of Contents

Preface     xiii
Introduction     1
Challenges     2
Previous Work     3
Contributions     4
Book Outline     7
References     8
Nano Devices and Architectures Overview     11
Nanoelectronic Devices     12
Carbon Nanotube-based Devices     12
Nanowires     14
Molecular Electronic Devices     15
Single-Electron Devices     17
Resonant Tunneling Diodes     21
Spin Transistors     22
Nano-scale Crossbars     23
Architectures     25
SET Architecture     26
RTD Architecture     26
NanoFabrics Architecture     27
NanoPLA     29
References     33
QCA     37
QCA Implementation     42
Metal QCA     42
Molecular QCA     44
Magnetic QCA     45
Clocking     45
Molecular Attachment     49
Power Gain and Dissipation     51
QCA Simulators     53
QCADesigner     54
QCA Circuits     56
Comparisonof Nanotechnology Devices     61
References     54
QCA Combinational Logic Design     69
Gate-based Combinational Logic Design     69
Gate-based Design of QCA with Existing Commercial Synthesis Tools     71
Logic Synthesis     73
And/Or-based Logic Synthesis     73
Muroga's MV-based Logic Synthesis     75
MAjority Logic Synthesizer (MALS)     75
Structural Design     75
And-Or-Inverter (AOI) Gate     76
AOI Gate Characterization     76
Defect Characterization of the AOI Gate     78
Logic Synthesis Using the AOI Gate     82
Conclusion     87
References     89
Logic-Level Testing and Defect Characterization     91
Logic-Level Testing     91
Stuck-at Test Properties of MV-based Circuits     92
Test Set for MVs     95
C-Testability of MV-based Designs     96
Defect Characterization of Devices     99
Simulation Engines     101
MV Defect Analysis     102
Interconnect Defect Analysis     107
Probabilistic Analysis and Testing     111
Defect Analysis and Testing of QCA Circuits      116
Scaling in the Presence of Defects     133
Conclusion     140
References     141
Two-Dimensional Schemes for Clocking/Timing of QCA Circuits     143
Clocking Analysis     144
Two-Dimensional QCA Clocking     146
Two-Dimensional Wave QCA Clocking     151
Examples of QCA Circuits     156
Feedback Paths     159
Simulation Results     160
2-to-1 Multiplexer     161
One-bit Full Adder     161
RS Flip-flop     161
Conclusion     162
References     168
Tile-Based QCA Design     171
QCA Design by Tiling     174
Fully Populated Grid Analysis     176
Tiles Based on 3 X 3 Grids     179
Orthogonal Tile     179
Double Fan-out Tile     183
Baseline Tile     187
Fan-in Tile     190
Triple Fan-out Tile     192
Analysis of Results     195
Configuration Selection     196
Logic Analysis     196
Examples of QCA Circuits     200
One-bit Full Adder     200
Parity Checker      201
2-to-4 Decoder     206
2-to-1 MUX     208
Conclusion     210
References     211
Sequential Circuit Design in QCA     213
RS Flip-flop and D Flip-flop in QCA     214
Defect Characterization of RS Flip-flop     216
Timing Constraints in QCA Sequential Design     219
Timing Constraints Using RS Flip-flops     220
Timing Constraints using D Flip-flops     221
Algorithm for Clocking Zone Assignment     221
Algorithm Outline     221
Algorithm Detail     223
Algorithm for Coplanar Device     226
Examples of QCA Circuits     227
Defect Characterization of QCA Sequential Circuits     229
Discussion and Conclusion     239
References     246
QCA Memory     247
Introduction     247
Review of QCA Memories     249
Parallel Memory Architecture     252
Proposed Parallel QCA Memory Design     252
Clocking Considerations     255
Discussion and Comparison     257
Simulations     261
Serial Memory Architecture     263
Memory Design by Tiling      263
Clocking and Timing     266
QCA Tiles     268
Simulation     271
Conclusion     285
References     285
Implementing Universal Logic in QCA     287
Universal Gate     288
Universal Gate Designs     289
And/Or-based Synthesis     290
MV-based Synthesis     290
Memory-based LUT     294
Multiplexer-based LUT     298
Discussion and Conclusion     301
References     302
QCA Model for Computing and Energy Analysis     305
Review on Reversible Computing     306
Mechanical Model     308
Model of QCA Cell     309
Steady State Energy of QCA Devices     312
Entropy and Dissipation Analysis     315
Operation of the Mechanical Cell     315
Landauer and Bennett Clocking Schemes     320
Conclusion     323
References     325
Fault Tolerance of Reversible QCA Circuits     327
Hardware Redundancy Techniques     328
Majority Multiplexing in QCA     333
Fault Tolerant Capacity     334
Restoration Speed of Multiplexing      336
Summary     338
Reversible Computing and Fault Tolerance     339
Energy Dissipation of a Reversible MV Multiplexing System     341
System Without Fault     341
Dissipation in Fault Correction     342
Conclusion     344
References     347
Conclusion and Future Work     349
Preliminary for QCA Mechanical Model     353
References     356
Validation of Mechanical Model     357
Validation of Static Energy Analysis     357
Validation of Dissipation Analysis     358
References     360
Energy Dissipation Analysis of Circuit Units     363
About the Authors     367