Verilog: Frequently Asked Questions: Language, Applications and Extensions / Edition 1

by Shivakumar S. Chonnad, Needamangalam B. Balachander

Overview

This book addresses "front end" questions and issues encountered in using the Verilog HDL, during all the stages of Hardware Design, Synthesis and Verification. The issues discussed in the book are typically encountered in both ASIC design projects as well as in Soft IP designs. These issues are addressed in a simple Q&A format. Since each issue is independently dealt with and explained in detail, this book acts as an important source of reference for the Verilog users. Each of the FAQs will be illustrated with figures and tables as required. The latest Verilog-2001 and SystemVerilog have also been referred to in this book.

With the increasing complexity of ASICs being designed these days, the decisions that one makes in any of the stages of Design, Synthesis or Verification has profound effects on these three stages. This book presents the intricacies of these inter-dependent issues in the context of the Verilog HDL.

Product Details

ISBN-13:	9781441919861
Publisher:	Springer New York
Publication date:	12/01/2010
Edition description:	Softcover reprint of the original 1st ed. 2004
Pages:	238
Product dimensions:	0.56(w) x 9.21(h) x 6.14(d)

Table of Contents

Basic Verilog.- RTL Design.- Verification.- Miscellaneous.- Common Mistakes.- Verilog During Simulation Regressions.